Controller IC Chip - SMSC MEC1310-NU MEC1310 NU I/O QFP-128 Chip for laptop - Integrated Laptop Chip (Code 1-CHIP1033)

Controller IC Chip - SMSC MEC1310-NU MEC1310 NU I/O QFP-128 Chip for laptop- Integrated portable calculator chip(SKU.1-CHIP1033)

The MEC1310 is a 128-pin 3.3V LPC-based ACPI 2.0 and PC99/PC2001 compliant Notebook I/O Controller. See FIGURE 1: MEC1310 Block Diagram on page 4. The MEC1310 incorporates a high-performance 8051- based keyboard and system controller with internal embedded 64K SRAM; a 1K byte Boot ROM, and 64- bytes battery backed registers. The embedded 64K SRAM is loaded via HOST/8051 SPI Memory Interface. The HOST/8051 SPI Memory Interface can be configured in Switched SPI Flash Configuration or Parallel Shared SPI Flash Configuration. The MEC1310 has four PS/2 ports; an 16C550A-compatible 2 pin UART for Debug Port; three 8584-style I 2C/SMBus controllers with two selectable ports per controller; a Serial IRQ peripheral agent interface; three ACPI Embedded Controller Interface; General Purpose I/O pins and seven General Purpose Outputs; four independently programmable pulse width modulators; dual fan control through the implementation of two fan tachometer input pins, RPM-PWM block with one tachometer input and one PWM output; hardware monitoring of a PWM input and maskable hardware wakeup events; one BC-Link Combined High Speed/Low Speed Bus Master Controller; 5 channel Analog to Digital Converter. The MEC1310 has two separate power planes to provide “instant on” and system power management functions. Additionally, the MEC1310 incorporates sophisticated power control circuitry (PCC). The PCC supports multiple low power down modes. Wake-up events and ACPI-related functions are supported through the SCI Interface. The MEC1310 supports the ISA Plug-and-Play Standard (Version 1.0a) and provides all the functionality for current Windows O/S’s. The I/O Address and Hardware IRQ of each logical device in the MEC1310 may be reprogrammed through the internal configuration registers. There are 480 I/O address location options and 15 IRQs for each logical device.

3.3V Operation with 5V Tolerant Buffers on PS/2 pins • ACPI 1.0/2.0 PC99/PC2001 Compliant • LPC Interface with Clock Run Support - Supports LPC Bus frequencies of 19.2MHz to 33MHz - Serial IRQ Interface Compatible with Serialized IRQ Support for PCI Systems - 15 Direct IRQs - ACPI SCI Interface - nSMI output and supporting PM registers - Shadowed write only registers • Internal 64K SRAM in MEC1310 - Loaded at VCC1 power from the HOST/8051 SPI Memory Interface - Provides 64KB of 8051 program space - 32k-Byte region shared with 8051data space • HOST/8051 SPI Memory Interface - 3-pin Full Duplex serial communication interface. - One Chip Select Pins - Fully 8051 Controlled - Hardware Support for two SPI Flash Configurations: – Switched SPI Flash Configuration – Parallel Shared SPI Flash Configuration – Debug Programming Interface • Two Power Planes - Low Standby Current in Sleep Mode • Three ACPI Embedded Controller Interface • Configuration Register Set Compatible with ISA Plug-and-Play Standard (Version 1.0a) • High-Performance Embedded 8051 Keyboard and System Controller - Provides System Power Management - System Watch Dog Timer (WDT) - 8042 Style Host Interface - Supports Interrupt and Polling Access - 1024 Boot /ROM - 256 Bytes Data RAM - On-Chip Memory-Mapped Control Registers - Access to VCC0 Backed Registers - Up to 18x8 Keyboard Scan Matrix - Two 16-Bit Timer/Counters - Integrated Full-Duplex Serial Port Interface - Seventy-Three 8051 Interrupt Sources - Thirty-Two 8-Bit, Host/8051 Mailbox Registers - Sixty-Four Maskable Hardware Wake-Up Events - Fast GATEA20 - Fast CPU_RESET - Multiple Clock Sources and Operating Frequencies - IDLE and SLEEP Modes - Trace FIFO Debug Port • Accurate Fail-Safe Ring Oscillator - Single Clock source for most 8051 and SIO functions - Provides 2% frequency accuracy - Lock Bit provides status - 32.768KHz-input clock – Single ended input – Compatible with south bridge SUSCLK/ RSMRST# gating rules – replacement 32K distribution available when RSMRST# is asserted – Very low power state with only external 32K clock distributed • Integrated Standby Power Reset Generator - VCC1_RST# open drain output - Accepts External driven Reset • VCC0 Backed Resources - 64 Byte VCC0 Backed Registers - VCC0 Backed Status Register • Three 8584-Style I2C/SMBus Controllers - 8051 Controlled Logic Allows I2C/SMBus Master or Slave Operation - I2C/SMBus Controllers are Fully Operational on Standby Power - Two Controllers with 2 Sets of Dedicated Pins per I2C/SMBus Controller - One Controller with one Set of Dedicated Pins per I2C/SMBus Controller • Four independent Hardware Driven PS/2 Ports - GPIO signal function associated with each pin • PECI Interface 2.0 • 56 General Purpose I/O Pins - Maskable Hardware Wake-Event Capable - Programmable Open-Drain/Push-Pull Outputs • 7 General-Purpose Outputs • Four Programmable Pulse-Width Modulator Outputs - Independent Clock Rates - 6-Bit Duty Cycle Granularity - Operational in both Full on and Standby modes • Dual Fan Tachometer Inputs • RPM-Based Fan Speed Control Algorithm - Utilizes one TACH input and one PWM output - 3% accurate from 500 RPM to 16k RPM - Automatic Tachometer feedback - Aging Fan or Invalid Drive Detection - Spin Up Routine - Ramp Rate Control – RPM-based Fan Speed Control Algorithm • Debug Port (UART) - High-Speed 16550A-Compatible UART with 16-Byte Send/Receive FIFOs - Programmable Baud Rate Generator - Relocatable to 480 Different Base I/O Addresses - 15 IRQ Options • BC-Link Interconnection Bus - Combined High Speed/Low Speed Bus Master Controller • General Purpose Analog to Digital Converter (GPADC) - 10-bit conversion precision - 10-bit conversion per channel is completed in 10.91us - 5 ADC channels – 10-bit Conversion with 25.78 mV resolution – 0 to 3.3 VDC Conversion Range - Channel 0 has a 5 volt tolerant input - Optional continuous sampling at a programmable rate - Selectable VREF source on a per Channel Basis.

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