Controller IC Chip - SMSC MEC1633L-AUE 1633L-AUE BGA IO Chip for laptop - Integrated Laptop Chip (Code 1-CHIP1036)

Controller IC Chip - SMSC MEC1633L-AUE 1633L-AUE BGA IO Chip for laptop- Integrated portable calculator chip(SKU.1-CHIP1036)

The MEC1633 is the mixed signal base component of a multi-device advanced I/O controller architecture. The MEC1633 incorporates a high-performance 32-bit ARC 625D embedded microcontroller with a 192 Kilobyte Embedded Flash Subsystem, 16 Kilobytes of SRAM, 1 Kilobyte EEPROM emulation, and a 2 Kilobyte EEPROM. The MEC1633 communicates with the system host using the Intel® Low Pin Count bus. The MEC1633 is the EC Base Component of a split-architecture Advanced I/O Controller system which uses BC-Link communication protocol to access up to three companion components. The BC-Link protocol is peer-to-peer providing communication between the MEC1633 embedded controller and registers located in a companion. The MEC1633 is directly powered by two separate suspend supply planes (VBAT and VTR) and senses a third runtime power plane (VCC) to provide “instant on” and system power management functions. The MEC1633 also contains an integrated VTR Reset Interface and a system Power Management Interface that supports low-power states and can drive state changes as a result of hardware wake events as defined by the MEC1633 Wake Interface. The MEC1633 defines a software development system interface that includes an MCU Serial Debug Port, a two pin serial debug port with a 16C550A register interface that is accessible to the EC or to the LPC host and can operate up to 2 MB/s, a flexible Flash programming interface, a Port 80 BIOS Debug Port, Gang Programmer Interface, and a JTAG interface. The EC can also drive the JTAG interface as a master.

• 3.3V Operation • ACPI Compliant • LPC Interface • VTR (standby) and VBAT Power Planes - Low Standby Current in Sleep Mode • Configuration Register Set - Compatible with ISA Plug-and-Play Standard - EC-Programmable Base Address • ARC-625D Embedded Controller (EC) - 16 KB Single Cycle 32-bit Wide Dual-ported SRAM, Accessible as Closely Coupled Data Memory and Instruction Memory - 4KB Boot ROM - 32 x 32 → 64 Fast Multiply - Divide Assist and Saturation Arithmetic - Maskable Interrupt Aggregator/Accelerator Interface - Maskable Hardware Wake-Up Events - Sleep mode - JTAG Debug Port, Includes JTAG Master - MCU Serial Debug Port - 1ms Delay Register - 10-Channel DMA Interface Supports SMBus Controllers and EC/Host GP-SPI Controllers • Embedded Flash - 192 KB user space, 32-bit Access, 10 K Cycles Endurance - Flash Security Enhancements – 4K Boot Block Protection – Direct JTAG and Direct LPC-protected (2) Pages at or Near Top of Memory for Password Protection - Multiple Flash Programming Options – JTAG programmable – BIOS programmable – Programmable by EC at Power-on Using UART – Programmable on a Gang Programmer via Gang-programmer Interface • Embedded Non-volatile Read/Write Memory - 2 KB of EEPROM, Single Byte Access, 250K Cycles Endurance - 8-byte Block Erasable, 128 Blocks - Independent of main Flash memory • Legacy Support - Fast GATEA20 & Fast CPU_RESET • System to EC Message Interfa - Embedded Memory Interface – Host Serial or Parallel IRQ Source – Provides Two Windows to On-Chip SRAM for Host Access – Two Register Mailbox Command Interface – Host Access of Virtual Registers WITHOUT EC Intervention - Mailbox Registers Interface – Thirty-two 8-Bit Scratch Registers – Two Register Mailbox Command Interface – Two Register SMI Source Interface - ACPI Embedded Controller Interface – Four Instances – 1 or 4 Byte Data transfer capable – Full-duplex Register Access - ACPI Power Management Interface – SCI Event-Generating Functions • Battery Backed Resources - Power-Fail Status Register - 32 KHz Clock Generator - Week Alarm Timer Interface with Programmable Wake-up from 1ms to 45 Days - VBAT-Powered Control Interface – Six Wake-up Input Signals – Optional Latching of Wake-up Inputs - VBAT-Backed 64 Byte Memory • Four EC-based SMBus 2.0 Host Controllers - Allows Master or Dual Slave Operation - Controllers are Fully Operational on Standby Power - DMA-driven I2C Network Layer Hardware - I2C Datalink Compatibility Mode - Multi-Master Capable - Supports Clock Stretching - Programmable Bus Speed up to 400KHz - Hardware Bus Access “Fairness” Interface - SMBus Time-outs Interface - AMD-TSI Port - 12 Ports Assignable to Any Controller - 3 SMBus Isolation Switches – Three Pairs of Ports Can Be Joined • PECI Interface 3.0 • 18 x 8 Interrupt Capable Multiplexed Keyboard Scan Matrix - Optional Push-Pull Drive for Fast Signal Switching • Three independent Hardware Driven PS/2 Ports - Fully functional on Main and/or Suspend Power - PS/2 Edge Wake Capable.

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